Photomask quality estimation system and method for use in manufacturing of semiconductor device, and method for manufacturing the semiconductor device

ABSTRACT

A photomask quality estimation system comprises a measuring unit, a latitude computation unit and an estimation unit. The measuring unit measures the mask characteristic of each of a plurality of chip patterns formed on a mask substrate. The latitude computation unit computes the exposure latitude of each chip pattern based on the mask characteristic. The estimation unit estimates the quality of each chip pattern based on the exposure latitude.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-188678, filed Jun. 28, 2005,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a technique for estimating the qualityof a photomask used for manufacturing a semiconductor device, and morespecifically to a photomask quality estimation system and method, and amethod for manufacturing the semiconductor device.

2. Description of the Related Art

In accordance with the progress of microfabrication of semiconductordevices, there is a demand for further enhancement in the accuracy oflithography. To meet the demand, much stricter dimensional accuracy isnow being required for the photomasks used for lithography. Forinstance, there is a demand for reducing the tolerance in mask planardimensions to 10 nm or less, and more desirably, to 5 nm or less.Photomasks are manufactured by forming a resist pattern on a mask blank,and etching the shade film of the mask blank into a plurality of chippatterns. When, for example, a halftone phase-shift mask as a kind ofphotomask is produced, estimations concerning a number of check items,such as dimensional variation, phase difference, transmittance, andexistence/non-existence of a defect, are performed to estimate thequality of the mask.

However, in the prior art, since all mask patterns included in the chippatterns of a photomask are regarded as a population for qualityestimation, even if only some of the chip patterns are non-compliant andthe other chip patterns are compliant, the photomask is considereddefective. This makes the yield of photomasks extremely low, regardlessof the progress in the accuracy of the photomask manufacturing technique(see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-72440).

BRIEF SUMMARY OF THE INVENTION

In accordance with a first aspect of the invention, there is provided aphotomask quality estimation system comprising: a measuring unit whichmeasures a mask characteristic of each of a plurality of chip patternsformed on a mask substrate; a latitude computation unit which computesan exposure latitude of said each chip pattern based on the maskcharacteristic; and an estimation unit which estimates quality of saideach chip pattern based on the exposure latitude.

In accordance with a second aspect of the invention, there is provided aphotomask quality estimation method comprising: measuring a maskcharacteristic of each of a plurality of chip patterns formed on a masksubstrate; computing an exposure latitude of said each chip patternbased on the mask characteristic; and estimating quality of said eachchip pattern based on the exposure latitude.

In accordance with a third aspect of the invention, there is provided amethod for manufacturing a semiconductor device, comprising: forming aplurality of chip patterns on a mask substrate; measuring a maskcharacteristic of each of a plurality of chip patterns formed on themask substrate; computing an exposure latitude of said each chip patternbased on the mask characteristic; estimating quality of said each chippattern based on the exposure latitude; projecting images of the chippatterns onto a resist film coated on a semiconductor substrate to forma resist pattern on the semiconductor substrate; and forming, on thesemiconductor substrate, a plurality of circuit patterns correspondingto the chip patterns, using the resist pattern as a mask.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram illustrating a photomask quality estimationsystem according to an embodiment of the invention;

FIG. 2 is a schematic view illustrating an image reduction exposure unitemployed in the photomask quality estimation system of the embodiment;

FIG. 3 is a plan view illustrating a photomask employed in theembodiment of the invention;

FIG. 4 is a schematic view illustrating a writing unit employed in thephotomask quality estimation system of the embodiment;

FIG. 5 is a table illustrating a first estimation master for thephotomask;

FIG. 6 is a table illustrating a second estimation master for thephotomask;

FIG. 7 is a table illustrating a third estimation master for thephotomask;

FIG. 8 is a table illustrating a fourth estimation master for thephotomask;

FIG. 9 is a table illustrating a fifth estimation master for thephotomask;

FIG. 10 is a table illustrating a sixth estimation master for thephotomask;

FIG. 11 is a table illustrating a seventh estimation master for thephotomask;

FIG. 12 is a table illustrating an eighth estimation master for thephotomask;

FIG. 13 is a table illustrating a ninth estimation master for thephotomask;

FIG. 14 is a table illustrating a tenth estimation master for thephotomask;

FIG. 15 is a graph useful in explaining the exposure latitude of theembodiment;

FIG. 16 is a table illustrating an exposure latitude master employed inthe embodiment;

FIG. 17 is a first graph illustrating the electrical characteristic ofcircuit patterns employed in the embodiment;

FIG. 18 is a second graph illustrating the electrical characteristic ofcircuit patterns employed in the embodiment;

FIG. 19 is a flowchart illustrating a photomask quality estimationmethod employed in the embodiment; and

FIG. 20 is a flowchart illustrating a method of manufacturing asemiconductor device employed in the embodiment.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the invention will be described with reference to theaccompanying drawings. In the drawings, like reference numbers denotelike elements. The following embodiment just exemplifies the apparatusand methods for embodying the technical idea of the present invention,and the invention is not limited to the embodiment. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe technical idea.

As shown in FIG. 1, the photomask quality estimation system of theembodiment comprises a writing unit 4, CD (critical dimension)measurement unit 16, phase-difference measurement unit 36, transmittancemeasurement unit 56 and central processing unit (CPU) 300. The writingunit 4 writes a plurality of chip patterns on a mask substrate. The CDmeasurement unit 16 measures the mask characteristics of each of thechip patterns. The “mask characteristics” indicate each CD (criticaldimension), phase difference and transmittance of the chip patterns,etc. The CPU 300 includes a latitude computation section 309 andestimation section 310. The latitude computation section 309 computesthe exposure latitude of each of the chip patterns based on the maskcharacteristics. The estimation section 310 estimates the quality levelsof the chip patterns based on the computed exposure latitude. Theexposure latitude will be described later.

A photomask, whose quality is to be estimated by the photomask qualityestimation system, is inserted into the exposure unit shown in FIG. 2.The exposure unit comprises an illumination optical system 14, reticlestage 51, optical projection system 42 and wafer system 32.

The illumination optical system 14 includes an illumination source 41,aperture stop holder 58, polarizer 59, optical convergence system 43 andslit holder 54. The illumination source 41 emits illumination light,such as an argon fluoride laser beam, having a wavelength of, forexample, 193 nm. The aperture stop holder 58 is located below theillumination source 41. The polarizer 59 polarizes the illuminationlight emitted from the illumination source 41. The optical convergencesystem 43 converges the illumination light. The slit holder 54 islocated below the optical convergence system 43. The reticle stage 51 islocated below the slit holder 54. The optical projection system 42 islocated below the reticle state 51. The wafer system 32 is located belowthe optical projection system 42.

The reticle stage 51 comprises a reticle XY stage 81, reticle movableshafts 83 a and 83 b placed on the reticle XY stage 81, and reticleZ-inclination stage 82 connected to the reticle XY stage 81 by thereticle movable shafts 83 a and 83 b. The reticle stage 51 is connectedto a reticle-stage-driving unit 97. The reticle-stage-driving unit 97horizontally scans the reticle XY stage 81, and vertically drives thereticle movable shafts 83 a and 83 b. Accordingly, the reticleZ-inclination stage 82 can be horizontally positioned by the reticle XYstage 81, and also can be inclined with respect to the horizontaldirection by the reticle movable shafts 83 a and 83 b. A reticle movablemirror 98 is provided at an end of the reticle Z-inclination stage 82.The position of the reticle Z-inclination stage 82 is measured by areticle laser interferometer 99 opposing the reticle movable mirror 98.

As shown in FIG. 3, a photomask having a plurality of chip patterns 21to 29 is placed on the reticle stage 51. The chip patterns 21 to 29 areformed by etching a shade film 2 made of, for example, chrome (Cr), andhence include transmissive regions and shade regions. The transmissiveregions are used to form a plurality of equivalent patterns on a wafer,such as a silicon (Si) wafer. Accordingly, the chip patterns 21 to 29are identical in design. NAND devices, for example, are manufactured byprojecting the chip patterns 21 to 29. In NAND devices, it is requiredto reduce the range of variations in characteristics and dimensions.Trimming described later, for example, can adjust the averagecharacteristics of products.

A wafer coated with a resist film, onto which images of the chippatterns 21 to 29 shown in FIG. 3 are projected, is placed on the waferstage 32 shown in FIG. 2. The resist film may be formed of aphotosensitive material such as a positive or negative photoresist. Thewafer stage 32 shown in FIG. 2 comprises a wafer XY stage 91, wafermovable shafts 93 a and 93 b placed on the wafer XY stage 91, and waferZ-inclination stage 92 connected to the wafer XY stage 91 by the wafermovable shafts 93 a and 93 b. The wafer stage 32 is connected to awafer-stage-driving unit 94. The wafer-stage-driving unit 94horizontally scans the wafer XY stage 91, and vertically drives thewafer movable shafts 93 a and 93 b. Accordingly, the wafer Z-inclinationstage 92 can be horizontally positioned by the wafer XY stage 91, andalso can be inclined with respect to the horizontal direction by thewafer movable shafts 93 a and 93 b. A wafer movable mirror 96 isprovided at an end of the wafer Z-inclination stage 92. The position ofthe wafer Z-inclination stage 92 is measured by a wafer laserinterferometer 95 opposing the wafer movable mirror 96.

The photomask including the chip patterns 21 to 29 shown in FIG. 3 isproduced by the coating unit 3, writing unit 4, developing unit 7 andetching unit 5. The coating unit 3 is, for example, a spin coating unitfor coating a resist film on a mask substrate that is formed of, forexample, quartz glass and has the shade film 2 deposited thereon. Thewriting unit 4 includes a charge beam emission mechanism 230 and controlunit 301. The etching unit 5 etches the shade film using the mask resistpattern as an etching mask, thereby forming a plurality of chip patternson the mask substrate. The mask resist film may be made of aphotosensitive material, such as a positive or negative photoresist.

As shown in FIG. 4, the charge beam emission mechanism 230 includes anelectron gun 101 for emitting a charge beam. A first condenser lens 103and second condenser lens 104 are provided below the electron gun 101.When a charge beam passes through the first condenser lens 103 andsecond condenser lens 104, the current density and Kohler illuminationcondition of the charge beam are adjusted. A first forming apertureplate 105 is provided below the second capacitor lens 104. The firstforming aperture plate 105 controls the size of the charge beam. A firstprojector lens 106 and second projector lens 107 are provided below thefirst forming aperture plate 105. A second forming aperture plate 108 isprovided below the second projector lens 107. The image formed bypassing the charge beam through the first forming aperture plate 105 isguided to the second forming aperture plate 108. The second formingaperture plate 108 controls the size of the charge beam. A reductionlens 110 and object lens 111 are provided below the second formingaperture plate 108. A movable stage 116 for holding the mask substrate112 is provided below the object lens 111.

The mask substrate 112 is coated with a mask resist film sensitive tothe charge beam by the coating unit 3 shown in FIG. 1. The charge beampassing through the second forming aperture plate shown in FIG. 4 isreduced and projected onto the reverse surface of the mask resist filmof the mask substrate 112 via the reduction lens 110 and object lens111.

A blanking electrode 130 and blanking aperture plate 131 are interposedbetween the second condenser lens 104 and first forming aperture plate105. To stop the emission of a charge beam onto the mask resist film onthe mask substrate 112, the blanking electrode 130 deflects, onto thesurface of the blanking aperture plate 131, the charge beam passingthrough the second condenser lens 104 to prevent the charge beam fromreaching the mask resist film on the mask substrate 112. By stopping theemission of a charge beam onto the mask resist film on the masksubstrate 112 using the blanking electrode 130 and blanking apertureplate 131, the period of emitting the charge beam to the mask resistfilm on the mask substrate 112 is adjusted to thereby adjust theemission amount of the charge beam on the mask resist film. A formingdeflector 109 is interposed between the first and second projectorlenses 106 and 107. The forming deflector 109 deflects the charge beampassing through the first projector lens 106 to control the emissionposition of the charge beam on the second forming aperture 108. Anobject deflector 113 is provided near the object lens 111. The objectdeflector 113 deflects the charge beam guided through the first andsecond forming aperture plates 105 and 108 to scan the surface of themask resist film on the mask substrate 112.

The control unit 301 is connected to the charge beam emission mechanism230. The control unit 301 comprises a blanking amplifier 122, formingdeflection amplifier 120, object deflection amplifier 121, pattern datadecoder 123 and pattern data memory 124. The blanking amplifier 122applies a deflection voltage to the blanking electrode 130 to start andfinish the emission of a charge beam onto the mask resist film on themask substrate 112. This adjusts the amount of emission onto the maskresist film. The forming deflection amplifier 120 applies a deflectionvoltage to the forming deflector 109 to set the shape and size of thecharge beam applied to the mask resist film on the mask substrate 112.The object deflection amplifier 121 applies a deflection voltage to theobject deflector 113 to set the scanning position of the charge beam onthe mask resist film on the mask substrate 112. The pattern data memory124 stores the design data of the chip patterns 21 to 29 in the form of,for example, a CAD file. The pattern data decoder 123 shown in FIG. 4reads the CAD file from the pattern data memory 124, and instructs theforming deflection amplifier 120 and object deflection amplifier 121 towrite, on the mask resist film, a latent mask resist patterncorresponding to the chip patterns 21 to 29.

The developing unit 7 shown in FIG. 1 develops the mask resist film withthe latent mask resist pattern written thereon, thereby forming a maskresist pattern on the shade film 2. The etching unit 5 etches the shadefilm 2, using the mask resist pattern as an etching mask, therebyforming, on the mask substrate 112, such chip patterns 21 to 29 as shownin FIG. 3. A dry etching unit, for example, is used as the etching unit5.

A deep ultraviolet (DUV) microscope, for example, can be used as the CDmeasurement unit 16 shown in FIG. 1. The CD measurement unit 16 measureseach CD of each chip pattern 21 to 29 shown in FIG. 3, which is regardedas one of the mask characteristics. An optical thin-film characteristicmeasurement unit, for example, can be used as the phase-differencemeasurement unit 36 shown in FIG. 1. The phase-difference measurementunit 36 measures the phase differences of the chip patterns 21 to 29,which is regarded as another mask characteristic. A vacuum ultravioletspectroscope, for example, can be used as the transmittance measurementunit 56 shown in FIG. 1. The transmittance measurement unit 56 measureseach transmittance of each chip pattern 21 to 29, which is regarded asyet another mask characteristic.

The statistics unit 311 of the CPU 300 shown in FIG. 1 estimates, fromthe actual measurement values of appropriately extracted samples, thestandard deviations of the CDs, phase differences and transmittancesacquired when all mask patterns included in the chip patterns 21 to 29are regarded as a population. For instance, in the example of FIG. 5,the standard deviations of the CDs, phase differences and transmittancesacquired when all mask patterns included in the chip patterns 21 to 29are regarded as a population are 2.8, 1.8 and 0.11, respectively.Further, the statistics unit 311 of the CPU 300 shown in FIG. 1estimates, from the actual measurement values of appropriately extractedsamples, the standard deviations of the CDs, phase differences andtransmittances acquired when all mask patterns included in each of thechip patterns 21 to 29 are regarded as a population. For instance, inthe example of FIG. 6, the standard deviations of the CDs, phasedifferences and transmittances acquired when all mask patterns includedin the chip pattern 21 are regarded as a population are 2.1, 1.5 and0.09, respectively. Further, in the example of FIG. 7, the standarddeviations of the CDs, phase differences and transmittances acquiredwhen all mask patterns included in the chip pattern 22 are regarded as apopulation are 2.0, 1.4 and 0.09, respectively. Similarly, in theexample of FIG. 8, the standard deviations of the CDs, phase differencesand transmittances acquired when all mask patterns included in the chippattern 23 are regarded as a population are 2.2, 1.4 and 0.08,respectively. In the example of FIG. 9, the standard deviations of theCDs, phase differences and transmittances acquired when all maskpatterns included in the chip pattern 24 are regarded as a populationare 2.1, 1.3 and 0.07, respectively. In the example of FIG. 10, thestandard deviations of the CDs, phase differences and transmittancesacquired when all mask patterns included in the chip pattern 25 areregarded as a population are 1.6, 1.1 and 0.05, respectively. In theexample of FIG. 11, the standard deviations of the CDs, phasedifferences and transmittances acquired when all mask patterns includedin the chip pattern 26 are regarded as a population are 2.0, 1.2 and0.08, respectively. In the example of FIG. 12, the standard deviationsof the CDs, phase differences and transmittances acquired when all maskpatterns included in the chip pattern 27 are regarded as a populationare 2.8, 1.3 and 0.09, respectively. In the example of FIG. 13, thestandard deviations of the CDs, phase differences and transmittancesacquired when all mask patterns included in the chip pattern 28 areregarded as a population are 2.2, 1.3 and 0.09, respectively. In theexample of FIG. 14, the standard deviations of the CDs, phasedifferences and transmittances acquired when all mask patterns includedin the chip pattern 29 are regarded as a population are 2.2, 1.4 and0.09, respectively.

Based on the design data of the chip pattern 21 shown in FIG. 3, and thestandard deviations computed from the measured CDs, phase differencesand transmittances of the chip pattern 21, the latitude computationsection 309 computes, by optical simulation, the exposure latitude to beacquired when the chip pattern 21 is projected on a resist film usingthe exposure unit of FIG. 2. FIG. 15 shows the relationship between thedefocus points from the focus of the optical projection system 42 ofFIG. 2 and the changes in the CD of the projection image of the chippattern 21 shown in FIG. 3, acquired when the amount of exposure isvaried from a reference value by −0.7%, −0.34%, 0%, +3.4% and +7.0%. Itis understood from FIG. 15 that to secure a defocus margin of ±200 nmand a margin of ±5.0% concerning a change in the size of the projectionimage of the chip pattern 21, it is necessary to limit a change inexposure amount to the range of −3.4% to +3.4%, i.e., to less than 6.8%.The allowable range of changes in exposure amount set to secure adesired range of defocus points and a desired range of changes in thesize of the projection image of the chip pattern is called “exposurelatitude”. The latitude computation section 309 also computes theexposure latitude of each of the chip patterns 22 to 29.

The latitude computation section 309 further computes the exposurelatitude of all chip patterns 21 to 29. In the example of FIG. 16, theexposure latitude of all chip patterns 21 to 29 shown in FIG. 3 is 7.1%,and the exposure latitude degrees of the chip patterns 21 to 29 are6.8%, 6.5%, 6.7%, 6.6%, 6.5%, 6.8%, 6.6% and 6.7%, respectively.

The estimation section 310 shown in FIG. 1 estimates compares theexposure latitude of each of the chip patterns 21 to 29 with the upperlimit set for the exposure latitude of the photomask shown in FIG. 3,thereby estimating the quality of the photomask. For instance, when theupper limit value of the exposure latitude is 7.0%, the estimationsection 310 determines that the chip patterns 21 to 29 are acceptable inquality since their exposure latitude degrees are all less than 7.0%. Ifthe exposure latitude of a certain one of the chip patterns 21 to 29 isnot less than 7.0%, the estimation section 310 determines that thecertain chip pattern is unacceptable in quality.

A trim unit 201 connected to the CPU 300 measures the electricalcharacteristic of circuit patterns formed on a wafer by projecting, ontothe resist film of the wafer, the images of the chip patterns 21 to 29shown in FIG. 3, using the exposure unit shown in FIG. 2. Morespecifically, the trim unit 201 has a tester function for bringing aprobe card into contact with the pads of the wafer to supply test wavesto circuit patterns formed on the wafer, and measure the electricalcharacteristic output therefrom. If different electrical characteristicvalues are acquired from different circuit patterns, the trim unit 201performs a trimming process to make the circuit patterns have the sameelectrical characteristic.

If the measured CD of the chip pattern 21 is greater than that of thechip pattern 22, the CD of the circuit pattern acquired by projectingthe chip pattern 21 is greater than that of the circuit pattern acquiredby projecting the chip pattern 22. Further, if the measuredtransmittance of the chip pattern 21 is greater than that of the chippattern 22, the CD of the circuit pattern acquired by projecting thechip pattern 21 is greater than that of the circuit pattern acquired byprojecting the chip pattern 22, since the amount of exposure at theresist film of the wafer is greater in the circuit pattern correspondingto the chip pattern 21 than in the circuit pattern corresponding to thechip pattern 22. Accordingly, the circuit pattern corresponding to thechip pattern 21 has a lower electric resistance than the circuit patterncorresponding to the chip pattern 22. As a result, a response can beacquired from the circuit pattern corresponding to the chip pattern 21when a lower voltage is applied thereto, than from the circuit patterncorresponding to the chip pattern 22, as is shown in FIG. 17.Accordingly, based on the mask characteristics, such as the CDs andtransmittances, etc., of the chip patterns 21 to 29, the trim unit 201estimates a change (hereinafter referred to as a “trimming value”) inelectrical characteristic (e.g., electric resistance) acquired whenfuses included in the circuit patterns formed on the wafer are meltedand blown. Further, based on the differences in electricalcharacteristic between the circuit patterns, and the estimated trimmingvalues of the fuses, the trim unit 201 computes the number of fuses thatshould be melted and blown. The trim unit 201 makes the electricalcharacteristic values of the circuit patterns on the wafer identical toeach other by melting and blowing, using a laser or current, thecomputed number of fuses in each of the circuit patterns, as is shown inFIG. 18. Note that when wiring is formed by, for example, a damasceneprocess, the CD of a mask pattern does not correspond to that of thewiring formed on a wafer, therefore the trimming process performed bythe trim unit 201 is not limited to the above-described one.

The CPU 300 shown in FIG. 1 is connected to a dicing unit 202. Thedicing unit 202 cuts a wafer in a lattice of uniform squares, using ablade. The CPU 300 is also connected to a data-storing unit 320. Thedata-storing unit 320 comprises a measured-value-storing unit 305,statistic-storing unit 302, latitude-storing unit 303,allowable-value-storing unit 306, estimation-result-storing unit 307 andtest-result-storing unit 308.

The measured-value-storing unit 305 stores data concerning the CDs,phase differences and transmittances of the chip patterns 21 to 29measured by the CD measurement unit 16, phase-difference measurementunit 36 and transmittance measurement unit 56. The statistic-storingunit 302 shown in FIG. 1 stores the statistics masks shown in FIGS. 6 to14, which record the standard deviations of the CDs, phase differencesand transmittances of the chip patterns 21 to 29 computed by thestatistics unit 311. The latitude-storing unit 303 shown in FIG. 1stores the exposure latitude master which records the exposure latitudedegrees of the chip patterns 21 to 29 shown in FIG. 16 and computed bythe latitude computation unit 309. The allowable-value-storing unit 306shown in FIG. 1 stores an exposure latitude upper limit value used bythe estimation unit 310 to estimate the chip patterns 21 to 29. Theestimation-result-storing unit 307 shown in FIG. 1 stores qualityestimation results concerning the chip patterns 21 to 29, acquired bythe estimation unit 310. The test-result-storing unit 308 shown in FIG.1 stores the test results concerning the electrical characteristic ofthe circuit patterns, acquired by the trim unit 201.

The CPU 300 is further connected to an input unit 312, output unit 313,program-storing unit 330 and temporarily storing unit 331. The inputunit 312 may be formed of, for example, a pointing device, such as akeyboard or mouse. The output unit 313 may be formed of an image displayunit, such as a liquid crystal display or monitor, and a printer, etc.The program-storing unit 330 stores, for example, an operating systemfor controlling the CPU 300. The temporarily storing unit 331sequentially stores the operational results of the CPU 300. Recordingmediums for storing programs, such as semiconductor memories, magneticdisks, optical disks, magnetooptical disks, or magnetic tapes, are usedas the program-storing unit 330 and temporarily storing unit 331.

Referring now to the flowchart of FIG. 19, a photomask qualityestimation method employed in the embodiment will be described.

(a) At step S90, a mask substrate 112 with a shade film depositedthereon is prepared, and the shade film is coated with a mask resistfilm using the coating unit shown in FIG. 1. At step S91, the masksubstrate 112 is placed on the movable stage 116 of the charge beamemission mechanism 230 shown in FIG. 4. Subsequently, the pattern datadecoder 123 reads, from the pattern data memory 124, design data of thechip patterns 21 to 29 shown in FIG. 3, and instructs the blankingamplifier 122, forming deflection amplifier 120 and object deflectionamplifier 121 shown in FIG. 4 to write chip patterns on the mask resistfilm. The blanking amplifier 122, forming deflection amplifier 120 andobject deflection amplifier 121 apply deflection voltages to theblanking electrode 130, forming deflector 109 and object deflector 113,respectively, to deflect the charge beam emitted from the electron gun101, thereby writing, on the mask resist film, latent imagescorresponding to the chip patterns 21 to 29.

(b) At step S92, after the mask resist film is baked, it is developed bythe developing unit 7 using an alkali developer, thereby forming a maskresist pattern corresponding to the chip patterns 21 to 29.Subsequently, the mask substrate 112 is moved into the etching unit 5shown in FIG. 1. The etching unit 5 eliminates, by reactive ion etching,parts of the shade film using the mask resist pattern as an etchingmask, thereby forming the chip patterns 21 to 29 on the mask substrate112. Thus, a photomask is completed. After that, the mask resist film isseparated by ashing, and the mask substrate 112 is cleaned.

(c) At step S101, the CD measurement unit 16 shown in FIG. 1 measuresthe CDs of the chip patterns 21 to 29 shown in FIG. 3, and stores themin the measured-value-storing unit 305 shown in FIG. 1. At step S102,the phase-difference measurement unit 36 measures the phase differencesbetween the chip patterns 21 to 29, and stores them in themeasured-value-storing unit 305. At step S103, the transmittancemeasurement unit 56 measures the transmittances of the chip patterns 21to 29, and stores them in the measured-value-storing unit 305. At stepS104, the statistics unit 311 reads, from the measured-value-storingunit 305, all the measured CDs, phase differences and transmittances ofthe chip patterns 21 to 29. After that, the statistics unit 311 computesthe standard deviations of the CDs, phase differences andtransmittances, and stores them in a statistics master prepared for theentire surface of the photomask shown in FIG. 5.

(d) At step S105, the statistics unit 311 reads, from themeasured-value-storing unit 305, the measured CDs, phase differences andtransmittances of the chip pattern 21. Thereafter, the statistics unit311 computes the standard deviations of the CDs, phase differences andtransmittances of the chip pattern 21, and stores them in a statisticsmaster prepared for the chip pattern 21 shown in FIG. 6. The statisticunit 311 also computes the standard deviations of the CDs, phasedifferences and transmittances of the other chip patterns 22 to 29, andstores them in respective statistics masters prepared for the chippatterns 22 to 29 shown in FIGS. 7 to 14.

(e) At step S106, the latitude computation section 309 computes theexposure latitude of the entire surface of the photomask, based on thedesign data of the chip patterns 21 to 29 and the standard deviations ofthe CDs, phase differences and transmittances recorded in the statisticmaster for the entire surface of the photomask shown in FIG. 5. Thelatitude computation section 309 stores the computed exposure latitudeof the entire photomask surface in the exposure latitude master shown inFIG. 16. At step S107, the latitude computation section 309 furthercomputes the respective exposure latitudes of the chip patterns 21 to29, based on the design data of the chip patterns 21 to 29 and thestandard deviations of the CDs, phase differences and transmittancesrecorded in the statistic masters for the chip patterns 21 to 29 shownin FIGS. 6 to 14. The latitude computation section 309 stores thecomputed exposure latitudes of the chip patterns 21 to 29 in theexposure latitude master shown in FIG. 16.

(f) At step S108, the estimation unit 310 shown in FIG. 1 reads theupper exposure latitude limit from the allowable-value-storing unit 306.Assume here that the upper limit is 7.0%. Subsequently, the estimationunit 310 reads, from the exposure latitude master of FIG. 16, theexposure latitude of the entire photomask surface and the exposurelatitudes of the chip patterns 21 to 29. The estimation unit 310compares the exposure latitudes of the entire photomask surface and chippatterns 21 to 29 with the respective upper limit values. If theexposure latitude exceeds the upper limit, it is determined“unacceptable”, whereas if the former is lower than the latter, it isdetermined “acceptable”. Since in the example of FIG. 16, the exposurelatitude of the entire photomask surface is 7.1%, it is determined“unacceptable”. However, the exposure latitudes of the chip patterns 21to 29 are 6.8%, 6.5%, 6.7%, 6.6%, 6.1%, 6.5%, 6.8%, 6.6% and 6.7%,therefore are all determined “acceptable”. Accordingly, the estimationunit 310 estimates that the photomask is “usable”, and stores, in theestimation-result-storing unit 307, the determination results concerningthe exposure latitude and the estimation results concerning thephotomask. This is the termination of the photomask quality estimationmethod of the embodiment.

The photomask quality estimation system and method described withreference to FIGS. 1 to 19 can improve the yield of photomask products.In the prior art, to estimate the quality of a photomask, all maskpatterns included in the chip patterns 21 to 29 shown in FIG. 3 providedon the photomask are used as a population for exposure latitudecomputation. Accordingly, where the upper limit of the exposure latitudeis 7.0%, if the exposure latitude of the entire photomask surfaceexceeds 7.0%, the photomask is determined unusable. In contrast, at stepS107 of the photomask quality estimation method shown in FIG. 19, theexposure latitude of each of the chip patterns 21 to 29 is computed, andat step S108, it is determined whether each computed exposure latitudedoes not exceed the upper limit. Therefore, the photomask shown in FIG.16, which is determined “unusable” in the prior art, is determined“usable” in this embodiment, since the exposure latitude of each chippattern 21 to 29 does not exceed the upper limit. Namely, the photomaskquality estimation system and method described with reference to FIGS. 1to 19 improve the yield of photomask products.

Referring then to the flowchart of FIG. 20, a description will be givenof a method for manufacturing a semiconductor device using the photomaskquality estimation method of the embodiment.

(A) At step S151, a wafer is coated with a resist filth using thecoating unit 3. The wafer is then placed onto the wafer stage 32 of theexposure, unit shown in FIG. 2. At step S152, the photomask estimated“usable” by the estimation unit 310 of FIG. 1 is placed onto the reticlestage 51 of the exposure unit. After that, the illumination source 41emits illumination light to project images of the chip patterns 21 to 29of FIG. 3 onto the resist film of the wafer. At step S153, the resistfilm of the wafer is exposed to light, baked (PEB) and developed,thereby forming, on the wafer, a resist pattern corresponding to thechip patterns 21 to 29. At step S154, using the resist pattern as aprocess mask, a conductive layer and insulation layer are deposited onthe wafer, thereby forming a plurality of circuit patterns on the wafer.

(B) At step S201, the circuit patterns formed on the wafer are subjectedto pre-die-sorting. Specifically, the probe card of the trim unit 201shown in FIG. 1 is brought into contact with the pads, included in thecircuit patterns to apply a wave signal thereto, and stores, in thetest-result-storing unit 308, the electrical characteristic of thecircuit patterns output therefrom. At step S202, the trim unit 201 readsthe electrical characteristic of the circuit patterns from thetest-result-storing unit 308, and determines whether the read electricalcharacteristic is uniform. If the electrical characteristic is notuniform, the trimming values of the fuses included in the circuitpatterns are computed to eliminate the differences in electricalcharacteristic between the chip patterns 21 to 29, based on the measuredCDs, phase differences and transmittances of the chip patterns 21 to 29stored in the measured-value-storing unit 305.

(C) At step S203, based on the computed trimming values, the trim unit201 melts and cuts part of the fuses included in the circuit patterns,using a laser or current, thereby unifying the circuit patterns inelectrical characteristic. At step S204, the trim unit 201 performspost-die-sorting to confirm whether trimming is performed correctly.Specifically, the trim unit 201 brings the probe card into contact withthe pads included in the circuit patterns, and confirms whether theelectrical characteristic of the circuit patterns output in response tothe input wave signal is uniform. If it is confirmed that trimming hasbeen performed correctly, the wafer is subjected at step S205 to dicingperformed by the dicing unit 202, thereby producing a plurality ofsemiconductor chips having circuit patterns of an identical electricalcharacteristic. After that, the semiconductor chips are sealed inrespective packages, which is the completion of a plurality ofsemiconductor devices.

In the prior art, when a plurality of circuit patterns are subjected totrimming, the number of fuses to be melted and cut is determined basedon the trimming values computed from the designed values, withoutregarding variations in such values that occur during the process.However, the chip patterns 21 to 29 differ in mask characteristic asshown in FIGS. 6 to 14, therefore different trimming values areacquired. This being so, there is a case where even if the fusesdetermined from the trimming values that are computed from the designedvalues are melted and cut, differences in characteristic between thecircuit patterns are not eliminated. In contrast, in the semiconductordevice manufacturing method of the embodiment shown in FIG. 20, trimmingvalues are computed based on the mask characteristic of each of the chippatterns 21 to 29, and hence a change in the electrical characteristicdue to fuse cutting can be accurately estimated. Accordingly, the numberof fuses to be melted and cut can be accurately estimated, which enablesthe uniformity in electrical characteristic between a plurality ofcircuit patterns to be realized highly accurately.

As described above in detail, the embodiment of the invention canprovide a photomask quality estimation system and method, and asemiconductor-device-manufacturing method, which can accurately estimatethe quality of photomasks and hence enhance the yield of photomaskproducts.

Other Embodiments

The present invention is not limited to the above-described embodiment.Any one skilled in the art can realize various embodiments based on thetechniques taught by of the present invention, and can utilize thetechniques in various ways. For instance, the above-described photomaskquality estimation method can be realized as temporally successiveprocesses or operations. Accordingly, the photomask quality estimationsystem shown in FIG. 1 can execute the photomask quality estimationmethod shown in FIG. 19, using a computer program that instructs, forexample, the processors included in the CPU 300 to execute a pluralityof functions. A memory device, magnetic disk device, optical disk deviceand other devices that can record programs can be used as memorymediums. As described above, the present invention can include othervarious embodiments. Namely, the technical scope of the presentinvention is defined only by the structural elements specified in theappended claims.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative, embodimentsshown and described herein. Accordingly, various modifications may bemade without departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1.-20. (canceled)
 21. A method for manufacturing a semiconductor device,comprising: preparing a photomask, wherein the photomask includes aplurality of chip patterns formed on a mask substrate, the plurality ofchip patterns including identical chip patterns for forming thesemiconductor device, a mask characteristic of each of the plurality ofchip patterns is measured, an exposure latitude of said each chippattern is computed based on the mask characteristic, and quality ofsaid each chip pattern is estimated based on the exposure latitude, theestimating the quality including comparing the exposure latitude of saideach chip pattern with an upper limit set for the exposure latitude ofthe entire mask substrate, and determining whether the exposure latitudeof said each chip pattern is equal to or less than the upper limit; andforming a pattern on a substrate using said each chip pattern formed onthe mask substrate that satisfies the determination.
 22. The method formanufacturing a semiconductor device according to claim 21, wherein theforming the pattern includes projecting image of said each chip patternonto a resist film coated on the substrate to form a resist pattern onthe substrate; and the method further comprises forming a circuitpattern corresponding to said each chip pattern on the substrate, usingthe resist pattern as a mask.
 23. The method for manufacturing asemiconductor device according to claim 21, wherein the determiningwhether the exposure latitude of said each chip pattern is equal to orless than the upper limit determines that the quality of said each chippattern is acceptable when the exposure latitude of said each chippattern is equal to or less than the upper limit, and determines thatthe quality of said each chip pattern is unacceptable when the exposurelatitude of said each chip pattern is more than the upper limit.
 24. Themethod for manufacturing a semiconductor device according to claim 22,further comprising computing trimming values of a plurality of fusesincluded in the circuit pattern based on the mask characteristic of saideach chip pattern.
 25. The method for manufacturing a semiconductordevice according to claim 24, further comprising melting and cuttingpart of the fuses based on the trimming values to unify the circuitpattern in electrical characteristic.
 26. The method for manufacturing asemiconductor device according to claim 21, wherein the computing theexposure latitude includes estimating a standard deviation of values ofthe mask characteristic obtained when mask patterns included in saideach chip pattern are used as a population, based on actually measuredvalues of the mask characteristic of samples extracted from thepopulation, and the exposure latitude is computed based on the standarddeviation.
 27. The method for manufacturing a semiconductor deviceaccording to claim 21, wherein the mask characteristic includes at leastone of a CD (critical dimension) of said each chip pattern, a phasedifference of said each chip pattern, and a transmittance of said eachchip pattern.